Phase change memory (also known as phase change random access memory, PC-RAM) is a novel variable resistance non-volatile semiconductor memory. Compared with various kinds of semiconductor memory technologies of the day, it has advantages of low power consumption, high density, anti-radiation, non-volatility, high-speed read, long cycle life (>1013 times), device size scalability (nano-scale), high and low temperature resistance (−55° C. to 125° C.), vibration proof, anti-electronic interference and simple process (compatible with current integrated circuit processes) and thus is universally regarded as the most competitive one of the next generation of memories in industry, enjoying extensive market prospect.
Phase change memory employs chalcogenide material as memory medium, utilizing the Joule heat generated by electric pulse or light pulse to realize reversible phase change of phase change memory material between amorphous (high resistance) state and crystalline (low resistance) state so as to realize data write and erase operations, while data read operation is realized by discerning the resistance states.
Data readout circuit is necessary to read the dada (i.e., crystalline or amorphous state) that are stored in phase change memory and directly represented as low resistance state or high resistance state, so phase change memory functions by inputting low-value current or voltage into the phase change memory cell and then measuring the corresponding voltage or current under the control of read enable signal and data readout circuit.
Generally, the data readout circuit works by sending a small current (voltage) value to the phase change memory cell, then the bit line voltage (current) is to be read out, and if the bit line voltage is high (current is low), then the phase change cell is at high resistance state, i.e. “1”; if the bit line voltage is low (current is high), then the phase change cell is at low resistance state, i.e. “0”. During the read process, however, the current flowing through the phase change memory cell will cause the phase change memory cell to generate Joule heat, and if the Joule heat power is greater than the heat dissipation efficiency of phase change memory cell, the heat effect will affect the basic state of phase change memory cell; meanwhile, if the voltage difference between two terminals of the phase change memory cell is above certain threshold, internal carriers of phase change material will lead to breakdown effect with a surge of carriers, showing characteristics of low resistance state even though no phase change occurs at all. These two phenomena mentioned above are known as destructive readout phenomenon.
In order to avoid the above destructive readout phenomenon, data readout circuit shall meet the following requirements: readout current (voltage) shall be very small such that the power of generating Joule heat will not be over the heat dissipation efficiency of phase change memory cell; when selecting a properly high readout current (voltage) in a permitted range, it shall be ensured that the readout speed is too high for the Joule heat generated to lead to the basic state change of the cell, and that the maximum readout current (voltage) shall be lower than the breakdown threshold of internal carriers so as to avoid breakdown effect induced by internal carriers of phase change material.
The foregoing requirements can be met for phase change memory under ideal conditions. However, as to actual phase change memory, the presence of parasitic capacitor on bit line will meet the above requirements while, at the same time, incur more time for the operation of current (voltage) readout. Since data readout circuit can not properly read out the state of the phase change memory cell until the bit line capacitor is charged up by the readout current (voltage), the speed of phase change memory is greatly restricted.
Conventional mode of current readout (i.e., inputting a voltage to read the corresponding current) generally works in the way that the operation amplifier in negative feedback operation mode directly imposes the clamp voltage on the bit line where the phase change cell is situated, and then compares the clamp voltage and the reference voltage. However, due to the presence of parasitic capacitor on bit line and the limitation that the bit line voltage shall not be over the threshold voltage of phase change cell, the readout speed is significantly restricted. Meanwhile, if the resistance difference between the high resistance state and the low resistance state is low, the readout speed and the reliability of the readout data of said data readout circuit will be highly restricted.
Moreover, due to the influence of the parasitic capacitors on bit lines or at the terminals of readout circuit, the initial read status for the next time will be affected by the charge remaining on the terminals of the data readout circuit and on the bit lines during the process of continuous high-speed read, and thereby incurring data crosstalk.
Therefore, it is an urgent technical issue for those skilled in the art to improve the problems of time consuming data readout, low resolution between high and low resistance as well as potential crosstalk, and to promote the speed and data reliability of phase change memory.